1. Field of the invention
This invention relates to a buffer monitoring system and more especially a peripheral buffer monitoring system coupled to a microcomputer having at least one interrupt input port which has to capture/release the buffers frequently.
2. Brief description of the related art
A mapped Input/Output (I/O) control method or a memory mapped I/O control method is utilized in a microcomputer system. According to such a method, every peripheral I/O device is assigned to a corresponding special area in a memory field as its own buffer and is accessed by the microcomputer in the same way as a usual memory address.
If there are many I/O devices to be handled and memory areas of a memory field are assigned as their buffers, a special buffer controller is required to control their priority or buffer number to avoid a shortage of available memory areas and/or to control the total throughput of the system.
FIG. 1 shows a general block diagram of a conventional buffer control system coupled to a microcomputer system utilized in a data transmission/reception system. In this figure, a buffer controller (BC) 10 is operatively connected to peripheral I/O devices 12 for controlling their buffers, which are assigned in a memory (not shown). The buffer controller 10 which can store the number of available buffers and addresses of the buffers, and outputs a digital buffer number signal BN, representing the number of available buffers. An I/O controller (hereafter, IOC) 14 for controlling the I/O devices, receives the signal BN and if requested, writes predetermined data in the buffer and reads data from the buffer. A bus line 16, shown in partly omitted form in FIG. 1, connects main devices such as a read only memory ROM (not shown) a random access memory RAM (not shown) to each other and to a central processing unit 18 (hereafter, CPU) which provides overall control of the system.
In this system, the buffer controller 10 monitors the status of the I/O devices 12. If the buffer controller 10 receives a buffer request from an I/O device 12, the buffer controller 10 assigns the I/O device to an available buffer and subtracts 1 from the previously stored available buffer number which was initially set by the CPU 18, and rewrites the stored addresses of available buffers. On the other hand, if another I/O device releases its buffer, the buffer controller 10 adds 1 to the available buffer number.
As to the job of the CPU 18, whenever the CPU 18 has to know the number of available buffers, it has to read the number from the buffer controller 10 via the IOC 14 using an appropriate and conventional "READ" operation. Therefore, if the CPU 18 performs a special function such as controlling a telephone switching system having a large number of I/O devices, which need frequent exchanging and frequent capturing/releasing of buffers, the CPU 18 has to repeat such "READ" operations a number of times in a short interval, even if the number of available buffers has not changed, in order to manage the available buffers. Generally, READ/WRITE operations executed in a usual CPU, such as a microcomputer, consumes more execution time (clock cycles) than the other operations. This severely limits the total throughput of the system.
The invention is invented to eliminate the above limitation on system throughput.